Job Description: We are seeking a talented and motivated junior engineer for the position of VLSI Design Verification Junior. In this role, the successful candidate will develop UVM based verification environment , verification tests suite , and ultimately conduct end to end verification project  for complex digital design.  This includes developing advanced verification environment, test development , running regression , and debugging simulations.

Responsibilities:

Develop verification environment in System Verilog UVM
.Develop cohesive verification tests suite
.Debug simulations
.Collaborate closely with the design and architecture engineers

Requirements: 

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer science.
Strong analytical and problem-solving skills.
Good teamwork and interpersonal communication skills.
Familiarity with Object oriented programming languages.
Advantage: Familiarity with Hardware programming languages such as Verilog, System Verilog, or VHDL.
Advantage: Understanding of digital verification and various testing methodologies.
Advantage: Previous experience in VLSI or verification.

Additional Skills:

Fluent in English.
Knowledge of advanced verification techniques and infrastructure.
Familiarity with verification tools and software such as UVM.
High motivation to learn and grow in the field.